The Papilio FPGA Logic Analyzer (PLA) kit is a fully featured logic analyzer that has its roots in the Open Bench Logic Sniffer (OLS) project. We took all the tricks we learned from designing the FPGA side of the Logic Sniffer and applied them to the PLA, expanding the memory, increasing transfer speeds, providing 32 5V tolerant channels, and making it available for debugging internal FPGA designs. It's a highly capable platform which enables us to continue developing all of the Logic Analyzer features that just wouldn't fit in the Logic Sniffer. Not only is the PLA a very capable Logic Analzyer, it's also an awesome FPGA development board! You can use the Logic Analyzer to debug circuits by day, and use the Papilio FPGA to make System on Chip designs by night!